The performance characteristics of many linear and mixed signal integrated circuits are primarily dependent on the matching characteristics of current mirrors and differential amplifiers. In order to achieve a low offset voltage from an operational amplifier, the input transistors should be laid out identically. Otherwise, a DC offset may develop at the output of the circuit.
In many op-amp applications, it is desirable to minimize the variance of the op-amp input offset voltage. Assembly induced package stress is the key factor behind many assembly and test (A/T) yield problems for operational amplifier devices. The primary component for the assembly induced shifts is mold compound. The contracting of the compound causes stress on the active components of the op-amp, which creates large input offset voltage (VIO) variances. The wide swings in VIO introduce, in some cases, unacceptable yield losses during the final test.
In order to understand the impact of package stress, one should understand the key parameter of an op-amp, which is mostly affected by the stress. A general-purpose op-amp specifies an input offset voltage (VIO). This parameter is the DC voltage that must be applied to the input terminals to cancel the DC offset within the op-amp in order to force the quiescent DC output voltage to a specified level.
Further, an input offset mismatch in the input stage (i.e., transistors and other components) during the fabrication of the silicon die creates effects that produce a mismatch of the bias currents flowing through the input stage, which results in a differential voltage (Vd). The parameter VIO itself determines the accuracy of a particular op-amp's performance. In a typical application, the smaller the VIO, the better the performance characteristics. Most op-amps have a precision-mirrored, two-sided design input-stage. This reduces the changes in the output voltage, which ensures uniform changes due to stress levels.
Accordingly, careful planning of the design layout improves the performance of the VIO with respect to the package shift. One of the important aspects of the performance of differential amplifiers is the minimum DC differential voltage that can be detected. The presence of mismatched components within the amplifier itself and the drifts of its values with temperature produce differential voltages at the output. This causes the output signal to be unrecognizable from the signal being amplified. In most analog systems, this type of DC error is the basic limitation on the solution of the system.
Therefore, the consideration of mismatch-induced offsets is centralized to the design of analog circuits. The DC performance and the effects of mismatches are represented by the quantities of the input offset voltage and current.
Typically, the predominant causes of offset error, from a process viewpoint, lie in the emitter-coupled transistor pair. The mismatches are in the base width, base-doping level, and collector doping level of the transistors, and further are in the effective emitter area of the transistors and the collector load resistors.
Because silicon is piezoresistive (i.e., under stress, it exhibits resistivity changes), the variations in stress produce changes in resistor-matching across the die. Some layout techniques have been developed to minimize resistor stress sensitivity. A linear design can vary from one to the next, since different forms of packaging material produce different modulus (thermal) characteristics. The thermal expansion of plastic encapsulation is approximately ten times that of silicon. As the encapsulated package cools, it creates a difference between the coefficients of thermal expansion of silicon. This causes the epoxy to remain frozen in the packaged device, which generates “residual stresses”, as shown in FIGS. 1A-1C.
The input offset voltage measurements during pre- and post-package reveal differences, known as “package shifts”, which are proportional to the amount of the residual stresses. Package shift lowers the input offset voltage precision of the device, which raises test yield issues. Through the careful planning and layout of a linear design circuit, the sensitivity of the circuit can be configured so as to reduce the magnitude of the package shifts.
Conventional solutions related to the “package stress” problems include die potting, lower stress mold compounds, and pre-package trimming. However, there is no existing solution that provides a design layout recommendation, which takes “package shift” into consideration even before producing the material.
Therefore, a need exists to overcome the problems with the prior art as discussed above.